1. Field of the Invention
The present invention relates to a semiconductor memory device and method for manufacturing the same and, in particular, to a memory structure for a dynamic RAM (DRAM) and method for manufacturing the same.
2. Description of the Related Art
In recent years, a NAND type memory array structure has been proposed which includes a serial array of MOS transistors and information storage capacitors each connected to the source (or drain) of the MOS transistor. This structure is disclosed, for example, in K. Kimura et al. "A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture", 1991 ISSCC, pp 106-107. As a capacitor for such a memory array, a stacked type capacitor has usually been used.
FIG. 1 shows a planar layout of an ordinary stacked capacitor type memory array and FIG. 2 is a cross-sectional view as taken along line 2--2 in FIG. 1. Four MOS transistors T1, T2, T3, T4 and four capacitors C1, C2, C3, C4 are so provided between a bit line contact 111 and a field oxide film 103 at a semiconductor substrate that these transistors and capacitors are alternately arranged in that array. The MOS transistor is comprised of a gate 108 and source and drain regions 109 provided one at each side of the gate 108 in a surface portion of the semiconductor substrate 101 with a gate insulating film 107 formed therebetween. The transistors are connected in a serial array in such a manner that the source and drain regions are shared by the adjacent transistors. The capacitor has a capacitor electrode 106 on the source and drain regions 109 and a plate electrode 122 overlying the capacitor electrode 106 with a capacitor insulating film 121 provided therebetween. In FIG. 2, reference numerals 112 and 113 represent an insulating interlayer and a bit line, respectively.
In the NAND type memory cell array system having the serial array of the MOS transistors, one bit line contact has only to be provided relative to one memory cell array and it is only necessary to provide less number of the bit line contacts than in other memory cell systems so that a cell size becomes smaller.
With the above-mentioned memory cell structure, however, the following problems have been encountered. That is, since the capacitor is of a stacked type and the cell area is restricted to a small area, a very tall capacitor has to be formed so as to obtain a necessary storage capacity. For this reason, when an overlying connection layer, such as a bit line, is formed, a step on an underlying layer surface is as large as over 1 .mu.m, that is, a very large step is involved, so that the formation of an overlying connection layer has become very difficult.
As a means for solving the above-mentioned drawbacks of the stacked capacitor, proposals have been made to form a buried type capacitor on the bottom of a trench in the substrate and to form a vertical type transistor on the trench. Such a structure is shown, for example, in W. F. Richardson et al. "A Trench Transistor Cross-Point DRAM Cell", 1985 IEDM, pp 714-717. This memory cell structure uses a trench type capacitor and can advantageously obtain an adequate storage capacitor readily by forming a deep trench. However, there is the following problem with such memory cell structure. That is, the transistor used is of a vertical MOS type and, for this reason, the side surface of the trench formed by an RIE (reactive ion etching) method is used as a channel region. There is a possibility that the insulating property of the gate insulating film or transistor characteristics will be affected by a damaged layer formed on the side surface of the trench when RIE is performed.
With the NAND type memory cell array structure using the stacked type capacitor, it has been difficult to obtain an adequate storage capacity when a high integration density unit is formed. Further, a very large step or steps are formed on a underlying layer surface when an overlying connection layer, such as a bit line, is formed. Therefore, the manufacturing steps have become difficult.
It may be considered that the trench type capacitors should be used, but there is possibility that the property of the gate insulating film and characteristics of the transistor will be adversely affected by a damaged layer formed on the side surface of the trench.